SeaOtterAll works

WINDLASS

Engineering design · digital logic5/5 checks passedcleared

WINDLASS's accepted Verilator waveform showing reset, quadrature A and B, step pulses, and signed position
See it run

A debounced quadrature decoder and signed saturating position counter, taken from a real wrapping failure to seven green Verilator assertions.

What the checks read

Each line is the buyer's own wording, beside what the check run observed.

  • Deliver a file bundle containing the revision history, synthesizable SystemVerilog, the C++ testbench, the acceptance runner, the accepted VCD waveform, and the banked tool outputs.

    9 delivered files; agreed file bundle format

  • Acceptance is a Verilator testbench rerun that must report all seven named assertions green.

    7/7 assertions passed under Verilator

  • The delivered revB RTL must be lint-clean under verilator --lint-only -Wall; any warning is blocking.

    0 lint findings under Verilator 5.050

  • Bank a VCD waveform from the passing revB run with real value changes.

    4,689 timestamps; 8,170 value changes; no required signal missing

  • Run the same functional contract against a deliberately defective revA and bank the non-zero refusal, then show revB passing without changing an assertion or limit.

    revA exited 1 at saturation; revB exited 0 on the same 7 assertions

THE ACCEPTED WAVEFORM

The trace is the run

This plate was parsed from the accepted VCD. It shows reset, the one-cycle bounce storm that moved nothing, forward and reverse Gray sequences, and a direction reversal returning position to zero.

Accepted WINDLASS Verilator trace with reset, quadrature A and B, step pulses and signed position over the first 380 picoseconds
87,266 bytes · 4,689 timestamps · 8,170 value changes · sha256 73ce994b0691933ed9d2fa771ecb67a1488b2d69fe6c4443399e62a42a29aff9
sealed assertions
7 / 7
lint findings
0
bounce toggles refused
24
8-bit limits held
+127 / −128
2 stagesAsynchronous A/B inputs cross a two-flop synchronizer before logic reads them.
3 samplesA new contact state must repeat three consecutive samples before it becomes real.
Gray onlyOnly one-bit quadrature transitions count; a two-bit jump is ignored and surfaced.

RED FIRST

Revision A wrapped at the rail

The same seven assertions ran before and after the fix. Revision A failed only signed saturation; revision B changed the counter policy, not the bar.

revA · refused6 / 7

Counter wrapped: max=-124 min=123.

revB · accepted7 / 7

Counter saturated: max=127 min=-128.

ASSERT_FAIL A_SATURATE_MAX_MIN max=-124 min=123
SUMMARY assertions=7 failures=1

ASSERT_PASS A_SATURATE_MAX_MIN max=127 min=-128
SUMMARY assertions=7 failures=0

THE VERILATOR HARNESS

Seven named assertions, all green

The acceptance runner compiled the delivered SystemVerilog and C++ harness itself. No alternate simulator and no canned pass path exists.

A_RESET_MID_COUNT_ZERO

position returned to 0

pass
A_BOUNCE_STORM_REJECTED

24 one-cycle toggles; position stayed 0

pass
A_FORWARD_SEQUENCE_COUNTS

00→01→11→10→00; position +4

pass
A_REVERSE_SEQUENCE_COUNTS

00→10→11→01→00; position −4

pass
A_DIRECTION_REVERSAL_AT_BOUNDARY

00→01 then 01→00; position returned to 0

pass
A_SATURATE_MAX_MIN

exhaustive 8-bit campaign held +127 and −128

pass
A_ILLEGAL_JUMP_IGNORED

00→11 ignored; diagnostic asserted

pass

Verilator 5.050 2026-07-01 rev vUNKNOWN-built20260701 · acceptance 56e87e6c-4750-46ab-b0ab-3b57f6512356 · bundle bbd7ffad5c424fba637a386fe699a60db19c5443af50baa2b3e97aa015c0095d

SETTLED AFTER THE RUN

Five contract checks passed; then the ledger drew

The non-live PaymentIntent was re-read from Stripe TEST. Dispatch reran the delivered bundle, accepted all required checks, and posted a five-entry zero-sum ledger.

estimator quote
£1,292.50
maker kept
£965.63
ledger
5 rows · zero

pi_3U0rkXFFRbB25fA71iYaqVHv · Stripe TEST · livemode=false · all_required_pass

THE DELIVERED BYTES

RTL, harness, waveform, and outputs

Nine files entered the accepted bundle. The public trace plate is a later, separately receipted derivative of the banked VCD.

  • windlass_revA.sv3,151 bytes
  • windlass_revB.sv3,445 bytes
  • tb_windlass.cpp5,969 bytes
  • run_acceptance.py7,473 bytes
  • revA-testbench.txt6,279 bytes
  • revB-testbench.txt6,210 bytes
  • revB-lint.txt383 bytes
  • windlass-revB.vcd87,266 bytes
  • WINDLASS_DELIVERY.md1,186 bytes

THE ENGINEERING BOUNDARY

Simulation verifies logic, not the installed encoder

The exhaustive rail campaign uses an 8-bit parameter override so every boundary is reached; the delivered synthesizable default is 16 bits and is linted through the same RTL. This does not prove FPGA timing closure, pin constraints, metastability MTBF, analogue input conditioning, encoder wiring, mechanical backlash, or site safety. Those require the target device and the real winch.

docs/qa/artifacts/20260805-windlass/

How the money moved

Every step names the banked record it was read from.

  1. asked

    Five buyer-anchored checks sealed while every delivery path was still absent.

    5 checks

    1 banked record
    • docs/qa/artifacts/20260805-windlass/seal-receipt.json

  2. checked

    The unchanged Verilator harness refused revision A when its signed counter wrapped at both rails.

    6/7

    1 banked record
    • docs/qa/artifacts/20260805-windlass/work/windlass/evidence/revA-testbench.txt

  3. passed · 3 steps

    Revision B passed all seven assertions, linted with zero findings, and banked a changing VCD.

    7/7

    3 banked records
    • docs/qa/artifacts/20260805-windlass/work/windlass/evidence/revB-testbench.txt
    • docs/qa/artifacts/20260805-windlass/work/windlass/evidence/revB-lint.txt
    • docs/qa/artifacts/20260805-windlass/work/windlass/evidence/windlass-revB.vcd

  4. paid

    Dispatch accepted all required checks, then drew the quoted amount into a zero-sum ledger.

    £1,292.50

    3 banked records
    • docs/qa/artifacts/20260805-windlass/acceptance-receipt.json
    • docs/qa/artifacts/20260805-windlass/ledger-receipt.json
    • docs/qa/artifacts/20260805-windlass/stripe-test-receipt.json

Who made it

SeaOtter's Superteam

SeaOtter's own team — first-party work, labeled so. Every number on this page is read from the production receipts; the file that holds each one is named beside it.

  • RTL
  • Verilator harness
  • Acceptance + evidence

When it refuses

The deliberately defective first counter wrapped through its signed limits. The unchanged harness named the one failed assertion before revision B could pass.

ASSERT_FAIL A_SATURATE_MAX_MIN max=-124 min=123

the banked record

docs/qa/artifacts/20260805-windlass/work/windlass/evidence/revA-testbench.txt

£1,292.50settled

Price yours

A job like yours

Last bankedon a machine£2,225.93passed 2026-08-04

Your job prices on your own words — a fixed quote before any account.

Price a job like this →